View DG407DYZ-T_8545310.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 single 16-channel/differential 8-channel, cmos analog multiplexers dg406, dg407 the dg406 and dg407 monolithic cmos analog multiplexers are drop-in replacements for the popular dg506a and dg507a series devices. they each incl ude an array of sixteen analog switches, a ttl and cmos compatib le digital decode circuit for channel selection, a voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. these multiplexers feature lower signal on-resistance (<100 ) and faster transition time (t trans < 300ns) compared to the dg506a and dg507a. charge in jection has been reduced, simplifying sample and hold applications. the improvements in the dg406 series are made possible by using a high voltage silicon-gate process. an epitaxial layer prevents the latch-up associated with older cmos technologies. the 44v maximum voltage range permits controlling 30v p-p signals when operating with 15v power supplies. the sixteen switches are bilateral, equally matched for ac or bidirectional signals. the on-res istance variation with analog signals is quite low over a 5v analog input range. features ? on-resistance (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 ?low power consumption (p d ) . . . . . . . . . . . . . . . . . . <1.2mw ? fast transition time (max) . . . . . . . . . . . . . . . . . . . . . . . 300ns ? low charge injection ? ttl, cmos compatible ? single or split supply operation ? pb-free (rohs compliant) applications ? battery operated systems ? data acquisition ? medical instrumentation ? hi-rel systems ? communication systems ? automatic test equipment related literature ?technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? figure 1. typical application figure 2. 15 dual supply r on curves at various temperatures cpu adc dg406 buffer analog inputs mux +125c -40c -55c +25c +85c 0c v+ = 15v v- = -15v 80 70 60 50 40 30 20 10 0 -15 -10 -5 5 10 015 v d , drain voltage (v) r ds(on) , on-resistance (w) october 1, 2013 fn3116.11 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2000, 2004, 2006, 2009, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn3116.11 october 1, 2013 dg406, dg407 pin configurations dg406 (28 ld pdip, soic) top view dg407 (28 ld pdip, soic) top view v+ nc nc s 16 s 15 s 14 s 13 s 12 s 11 s 10 s 9 gnd nc a 3 d s 8 s 7 s 6 s 5 s 3 s 1 en a 0 a 1 a 2 v- s 4 s 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v+ d b nc s 8b s 7b s 6b s 5b s 4b s 3b s 2b s 1b gnd nc nc d a s 8a s 7a s 6a s 5a s 3a s 1a en a 0 a 1 a 2 v- s 4a s 2a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pin description dg406 (pdip, soic) dg407 (pdip, soic) symbol description 1 1 v+ positive power supply 2, 3, 13 3, 13, 14, nc no connect- no internal connection 4, 5, 6, 7, 8, 9, 10, 11 - s 16 thru s 9 source switch terminals (these pins can be an input or output) 12 12 gnd ground (0v) reference 14, 15, 16, 17 - a 3 thru a 0 logic control inputs - 15, 16, 17 a 2 thru a 0 logic control inputs 18 18 en active high digital input (when low device is disabled and all switches are turned off. when high the ax logic inputs determine which switch is turned on. 19, 20, 21, 22, 23, 24, 25, 26 - s1 thru s8 source switch terminals (the se pins can be an input or output) 27 27 v - negative power supply (single supply application this pin will be connected to ground.) 28 - d drain switch terminal (this pin can be an input or output) -2, 28d b , d a drain switch terminal (this pin can be an input or output) - 4, 5, 6, 7, 8, 9, 10, 11 s 1b thru s 8b source switch terminals b (these pins can be an input or output) - 19, 20, 21, 22, 23, 24, 25, 26 s 1a thru s 8a source switch terminals a (these pins can be an input or output)
3 fn3116.11 october 1, 2013 dg406, dg407 schematic diagram (typical channel) ordering information part number (notes 2, 4) part marking temp. range (c) package (pb-free) pkg. dwg. # dg406djz dg406djz -40 to +85 28 ld pdip (note 3) e28.6 dg406dyz dg406dyz -40 to +85 28 ld soic m28.3 dg406dyz-t (note 1) dg406dyz -40 to +85 28 ld soic tape and reel m28.3 dg407djz dg407djz -40 to +85 28 ld pdip (note 3) e28.6 dg407dyz dg407dyz -40 to +85 28 ld soic m28.3 DG407DYZ-T (note 1) dg407dyz -40 to +85 28 ld soic tape and reel m28.3 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. pb-free pdips can be used for through-hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. 4. for moisture sensitivity level (msl), please see device information page for dg406, dg407 . for more information on msl, please see tech brief tb363 v+ gnd a 0 a x en v- v ref level shift decode/ drive v+ v+ v- d s 1 s n
4 fn3116.11 october 1, 2013 dg406, dg407 truth tables functional diagrams dg406 dg407 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 d to decoder logic controlling both tiers of muxing address decoder 1 of 16 enable a 0 a 1 a 2 a 3 en s 2a s 3a s 4a s 5a s 6a s 7a s 8a s 1b s 2b s 3b s 4b s 5b s 6b s 7b s 8b d a to decoder logic controlling both tiers of muxing address decoder 1 of 8 enable a 0 a 1 a 2 en s 1a d b table 1. dg406 truth table a 3 a 2 a 1 a 0 en on switch xxxx0 none 00001 1 00011 2 00101 3 00111 4 01001 5 01011 6 01101 7 01111 8 10001 9 10011 10 10101 11 10111 12 11001 13 11011 14 11101 15 11111 16 table 2. dg407 truth table a 2 a 1 a 0 en on switch pair xxx0 none 0 0 0 1 1a, 1b 0 0 1 1 2a, 2b 0 1 0 1 3a, 3b 0 1 1 1 4a, 4b 1 0 0 1 5a, 5b 1 0 1 1 6a, 6b 1 1 0 1 7a, 7b 1 1 1 1 8a, 8b logic ?0? = v al < 0.8v. logic ?1? = v ah > 2.4v. x = don?t care.
5 fn3116.11 october 1, 2013 dg406, dg407 absolute maximum rating s thermal information v+ to v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0v gnd to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v digital inputs, v s , v d (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(v-) -2v to (v+) +2v or 20ma, whichever occurs first continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30ma peak current, s or d (pulsed 1ms, 10% duty cycle max) . . . . . . . . . . . . . . . . . . . . . . . . . 100ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical, note 5) ja (c/w) pdip package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp *pb-free pdips can be used for through-hole wave solder processing only. they are not intended for use in refl ow solder processing applications. caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. 6. signals on s x , d x , en or a x exceeding v+ or v- are clamped by internal diod es. limit diode current to maximum current ratings. electrical specifications test conditions: v+ = +15v, v- = -15v, v al = 0.8v, v ah = 2.4v unless otherwise specified. bold-face limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 7, 12) typ (note 8) max (notes 7, 12) units dynamic characteristics transition time, t trans (see figure 3) 25 - 200 300 ns full - - 400 ns break-before-make interval, t open (see figure 5) 25 25 50 - ns full 10 --ns enable turn-on time, t on(en) (see figure 4) 25 - 150 200 ns full - - 400 ns enable turn-off time, t off(en) 25 - 70 150 ns full - - 300 ns charge injection, q c l = 1nf, v s = 0v, r s = 0 25 - 40 - pc off-isolation, oirr v en = 0v, r l = 1k , f = 100khz (note 11) 25 - -69 - db logic input capacitance, c in f = 1mhz 25 - 7 - pf source off capacitance, c s(off) v en = 0v, v s = 0v, f = 1mhz 25 - 8 - pf drain off capacitance, c d(off) v en = 0v, v d = 0v, f = 1mhz dg406 25 - 160 - pf dg407 25 - 80 - pf drain on capacitance, c d(on) v en = 5v, v d = 0v, f = 1mhz dg406 25 - 180 - pf dg407 25 - 90 - pf digital input characteristics logic high input voltage, v inh full 2.4 --v logic low input voltage, v inl full - - 0.8 v logic high input current, i ah v a = 2.4v, 15v full -1 - 1 a logic low input current, i al v en = 0v, 2.4v, v a = 0v full -1 - 1 a analog switch characteristics drain-source on-resistance, r ds(on) v d = 10v, i s = + 10ma (note 9) 25 - 50 100 full - - 125 r ds(on) matching between channels, r ds(on) v d = 10v, -10v (note 10) 25 - 5 - %
6 fn3116.11 october 1, 2013 dg406, dg407 source off leakage current, i s(off) v en = 0v, v s = 10v, v d = + 10v 25 -0.5 0.01 0.5 na full -5 - 5 na drain off leakage current, i d(off) dg406 25 -1 0.04 1 na full -40 - 40 na dg407 25 -1 0.04 1 na full -20 - 20 na drain on leakage current, i d(on) v s = v d = 10v (note 9 ) dg406 25 -1 0.04 1 na full -40 - 40 na dg407 25 -1 0.04 1 na full -20 - 20 na power supply characteristics positive supply current, i+ v en = v a = 0v or 5v (standby) 25 - 13 30 a full - - 75 a negative supply current, i- 25 -1 -0.01 - a full -10 --a positive supply current, i+ v en = 2.4v, v a = 0v (enabled) 25 - 80 100 a full - - 200 a negative supply current, i- 25 -1 -0.01 - a full -10 --a electrical specifications test conditions: v+ = +15v, v- = -15v, v al = 0.8v, v ah = 2.4v unless otherwise specified. bold-face limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 7, 12) typ (note 8) max (notes 7, 12) units electrical specifications msingle supply test conditions: v+ = 12v, v- = 0v, v al = 0.8v, v ah = 2.4v, unless otherwise specified. parameter test conditions temp (c) min (notes 7, 12) typ (note 8) max (notes 7, 12) units dynamic characteristics switching time of multiplexer, t trans v s1 = 8v, v s8 = 0v, v in = 2.4v 25 - 300 450 ns enable turn-on time, t on(en) v inh = 2.4v, v inl = 0v, v s1 = 5v 25 - 250 600 ns enable turn-off time, t off(en) 25 - 150 300 ns charge injection, q c l = 1nf, v s = 6v, r s = 0 25 - 20 - pc analog switch characteristics analog signal range, v analog full 0 - 12 v drain-source on-resistance, r ds(on) v d = 3v, 10v, i s = -1ma (note 9) 25 - 90 120 r ds(on) matching between channels (note 6), r ds(on) 25 - 5 - % source off leakage current,i s(off) v en = 0v, v d = 10v or 0.5v, v s = 0.5v or 10v 25 - 0.01 - na drain off leakage current, i d(off) dg406 25 - 0.04 - na dg407 25 - 0.04 - na
7 fn3116.11 october 1, 2013 dg406, dg407 drain on leakage current, i d(on) v s = v d = 10v (note 9) dg406 25 - 0.04 - na dg407 25 - 0.04 - na power supply characteristics positive supply current (i+) (standby) v en = 0v or 5v, v a = 0v or 5v 25 - 13 30 a full - 13 75 a negative supply current (i-) (enabled) 25 -1 -0.01 - a full -5 -0.01 - a notes: 7. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maximum, is used in this data s heet. 8. typical values are for design only and are not production tested. 9. sequence each switch on. 10. r ds(on) = (r ds(on) (max) - r ds(on) (min)) r ds(on) average. 11. worst case isolation occurs on channel 8b due to proximity to the drain pin. 12. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperatur e limits established b y characterization and are not production tested. electrical specifications msingle supply test conditions: v+ = 12v, v- = 0v, v al = 0.8v, v ah = 2.4v, unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 7, 12) typ (note 8) max (notes 7, 12) units test circuits and waveforms figure 3a. dg406 test circuit f igure 3b. dg407 test circuit figure 3c. measurement points figure 3. transition time en a3 dg406 gnd a 2 a 1 s 1 s 2 - s 15 s 16 d v- v+ 10v v o 35pf 300 50 +15v +2.4v -15v a 0 10v logic input en a 0 dg407 gnd a 1 a 2 s 1b ? s 8b d b v- v+ 10v v o 35pf 300 50 +15v +2.4v -15v ? = s 1a - s 8a , s 2b - s 7b , d a 10v logic input logic input switch output v o 3v v s1b 50% t r < 20ns t f < 20ns t trans 50% 0v 0v v s8b t trans s 8 on 80% 80% s 1 on v s8 v s1
8 fn3116.11 october 1, 2013 dg406, dg407 figure 4a. dg406 test circuit f igure 4b. dg407 test circuit figure 4c. measurement points figure 4. enable switching times figure 5a. test circuit fig ure 5b. measurement points figure 5. break-before-make interval test circuits and waveforms (continued) en a3 dg406 gnd a 2 a 1 s 1 s 2 - s 16 d v- v+ -5v v o 35pf 300 50 +15v -15v a 0 logic input v in en a 0 dg407 gnd a 1 a 2 s 1b ? d a and d b v- v+ -5v v o 35pf 300 50 +15v -15v ? = s 1a - s 8a , s 2b - s 8b , d a logic input v in logic input switch output v o 3v v o 50% t r < 20ns t f < 20ns t on(en) 0v 50% t off(en) 90% 0v v in v o en a3 dg406 gnd a 2 a 1 all s d, v- v+ +5v (v s ) v o 35pf 300 50 +15v +2.4v -15v a 0 dg407 and d a d b logic input logic input switch output v o 3v v s t r < 20ns t f < 20ns t open 0v 0v 80%
9 fn3116.11 october 1, 2013 dg406, dg407 typical performance curves figure 6. r ds(on) vs v d and supply figure 7. r ds(on) vs v d and temperature figure 8. r ds(on) vs v d and supply figure 9. i d , i s leakage currents vs analog voltage figure 10. i d , i s leakage vs temperature figure 11. switching ti mes vs bipolar supplies 5v 8v 10v 12v 15v 20v 160 140 120 100 80 60 40 20 0 -20 -16 -12 -8 -4 0 4 8 12 16 20 v d , drain voltage (v) r ds(on) , on resistance ( ) +125c -40c -55c +25c +85c 0c v+ = 15v v- = -15v 80 70 60 50 40 30 20 10 0 -15 -10 -5 5 10 015 v d , drain voltage (v) r ds(on) , on-resistance ( ) v- = 0v v+ = 7.5v 10v 12v 15v 20v 22v 240 200 160 120 80 40 0 048121620 v d , drain voltage (v) r ds(on) , on-resistance ( ) -10 -5 5 10 015 v s , v d , source drain voltage (v) v+ = 15v, v- = -15v v s = -v d for i d(off) v d = v s(open) for i d(on) i s(off) dg406 i d(on) , i d(off) -15 120 80 40 0 -40 -80 -120 i d , i s , current (pa) dg407 i d(on) , i d(off) v+ = 15v, v- = -15v v s or v d = 10v i s(off) i d(on) , i d(off) 100na 10na 1na 100pa 10pa 1pa 0.1pa i d , i s , current (a) -55 -35 -15 5 25 45 65 85 105 125 temperature ( o c) 350 300 250 200 150 100 50 0 5101520 v supply , supply voltage ( v) time (ns) t trans t on(en) t off(en)
10 fn3116.11 october 1, 2013 dg406, dg407 figure 12. switching times vs single supply figure 13. off-isolation vs frequency figure 14. supply currents vs switching frequency figure 15. t on /t off vs temperature figure 16. switching threshold vs supply voltage typical performance curves (continued) 700 600 500 400 300 200 100 0 5101520 v+, supply voltage (v) time (ns) t trans t on(en) t off(en) v- = 0v 1k 10k 1m 100k 10m f, frequency (hz) 100 -140 -120 -100 -80 -60 -40 -20 isol (db) 0 100 1k 100k 1m 10k 10m f, frequency (hz) e n = 5v, a x = 0v or 5v i gnd 10 10 8 6 0 -4 -8 -10 i, current (ma) i+ i- 4 2 -2 -6 300 280 260 240 220 200 140 120 60 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) time (ns) 180 160 100 80 t trans t on(en) t off(en) v+ = 15v, v- = -15v 5101520 v supply , supply voltage ( v) 0 0 1 2 3 v a ,(v)
11 fn3116.11 october 1, 2013 dg406, dg407 die characteristics die dimensions: 2490m x 4560m x 485m metallization: type: sial thickness: 12k ? 1k ? passivation: type: nitride thickness: 8k ? 1k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout dg407 a 0 en a 1 a 2 nc gnd s 8a s 7a s 6a s 5a s 4a s 3a s 2a s 1a v- d a d b v+ s 8b s 7b s 6b s 5b s 4b s 3b s 2b s 1b
12 fn3116.11 october 1, 2013 dg406, dg407 die characteristics die dimensions : 2490m x 4560m x 485m metallization : type: sial thickness: 12k ? 1k ? passivation : type: nitride thickness: 8k ? 1k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout dg406 v- s 16 d nc v+ s 5 a 0 en s 7 s 6 s 5 s 4 s 3 s 2 s 1 a 1 a 2 a 3 gnd s 15 s 14 s 13 s 12 s 11 s 10 s 9
13 fn3116.11 october 1, 2013 dg406, dg407 about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change october 1, 2013 fn3116.11 converted to new intersil template. removed obsolete parts from ordering information as follows: dg406dj dg406dy dg406dy-t dg407dy dg407dj added p/n DG407DYZ-T to ordering information table. march 13, 2006 fn3116.9 redline release parts added to ordering information. september 17, 2004 fn3116.8 pb-free parts added. august 1, 2000 fn3116.6 initial release to web.
14 fn3116.11 october 1, 2013 dg406, dg407 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in ca se of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo seri es symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendicular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.250 - 6.35 4 a1 0.015 - 0.39 -4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 -5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00
15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn3116.11 october 1, 2013 for additional products, see www.intersil.com/en/products.html dg406, dg407 small outline plast ic packages (soic) a index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45o c h 0.25(0.010) b m m (1.50mm) (9.38mm) (1.27mm typ) (0.51mm typ) typical recommended land pattern m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 1, 1/13 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate bu rrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact .

▲Up To Search▲

Price & Availability of DG407DYZ-T

	To Download DG407DYZ-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .